Abstract
The explosive growth of Data Center (DC) traffic is putting strenuous requirements in DC operators, that must push the performance envelope of the underlying network infrastructure towards (i) high network and resource utilization (ii) high bandwidth (iii) low latency and (iv) high energy efficiency. In this context, optical interconnects arise as a promising technological candidate for future DC and High-Performance Computing (HPC) environments, aiming to replace electronic interconnects with high-bandwidth, low-power optical solutions across the DC and HPC network hierarchy. The main research contributions of this thesis revolved around the development of an Optical Packet Switch (OPS) architecture, towards addressing the problem of high-port, high-bandwidth, low-latency switching as well as the study and deployment of Silicon Photonics (SiPho) circuits, outlining a roadmap towards next generation optical switches and transceivers. At first, in view of meeting the networking require ...
The explosive growth of Data Center (DC) traffic is putting strenuous requirements in DC operators, that must push the performance envelope of the underlying network infrastructure towards (i) high network and resource utilization (ii) high bandwidth (iii) low latency and (iv) high energy efficiency. In this context, optical interconnects arise as a promising technological candidate for future DC and High-Performance Computing (HPC) environments, aiming to replace electronic interconnects with high-bandwidth, low-power optical solutions across the DC and HPC network hierarchy. The main research contributions of this thesis revolved around the development of an Optical Packet Switch (OPS) architecture, towards addressing the problem of high-port, high-bandwidth, low-latency switching as well as the study and deployment of Silicon Photonics (SiPho) circuits, outlining a roadmap towards next generation optical switches and transceivers. At first, in view of meeting the networking requirements in terms of port count and latency of disaggregated DC architectures, an optical switch named Hipoλaos (High Port λ-routed All Optical Switch) was proposed and demonstrated. Hipoλaos can efficiently integrate Spanke-based switching with Arrayed Waveguide Grating Router (AWGR)-based wavelength routing and optical feedforward buffering, towards providing high-port layouts with sub-μs latency. A functional 1024-port plane of the Hipoλaos switch was constructed and experimentally demonstrated, using 10 Gb/s unicast and multicast packets, revealing error-free operation for all cases. Moving however towards practical optical switch implementations, requires an integration approach, with the um-SOI platform standing out as a promising integration vehicle for the Hipoλaos architecture. To this end, the basic building block of optical feed forward buffering i.e. a Time Slot Interchanger (TSI), was proposed and experimentally validated for 10 Gb/s data packets, with the optical delay lines realized through um-SOI waveguides. Followingly, an integrated version of the Hipoλaos switch was proposed, relying on um-SOI circuitry for both buffering and wavelength routing. The prototype 9×9 switch employed um-SOI delay lines for buffering and a 3×3 Echelle Grating for routing and was experimentally evaluated using 10 Gb/s packets for both unicast and multicast modes, revealing error-free operation for all cases. Consequently, towards addressing the need of a low-cost, direct detection scheme, for interconnecting geographically distributed DCs, a 50 Gb/s SiPho O-band Ring Modulator (RM)-based optical transmitter co-packaged with a high-speed driver was proposed and presented. The transmitter achieved a record high bandwidth distance product of 2600 Gb-kms (50 Gb/s × 52 km) , featuring an Extinction Ratio (ER) of 4.15 dB and a power consumption of 40 mW. Finally, a 200 Gb/s and a 400 Gb/s SiPho optical transceiver (TxRx) were proposed and demonstrated, with the developed modules leveraging Wavelength Division Multiplexing (WDM) and the significant advantages of RM-based transmitters, in terms of footprint and energy consumption versus approaches based on Mach Zehnder Modulators (MZM). The 200 Gb/s module featured four 50 Gb/s channels, was co-packaged with SiGe drivers and transimpedance amplifiers (TIA) and exhibited a 4 pJ/bit energy efficiency. The scaled up 400 Gb/s TxRx version featured 8 channels with a channel spacing of 1.14 nm and achieved an average ER of 4.5 dB.
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