Abstract
This thesis proposes new optical systems that exploit Optical Interconnect and Optical Memory Technologies and synergizes them with processors in innovative Computing Architectures for increasing bandwidth and reducing energy consumption. The novel optically-enabled concepts proposed in this thesis are spanning from complete High Performance Computing network environments down to chip-scale multi-core computing architectures. At first, OptoHPC-Sim simulation platform is demonstrated which supports the system‑scale utilization of novel electro‑optical boards and routing technologies in complete and fully operational High Performance Computing network architectures. By using OptoHPC-Sim, an optical board-based High Performance Computing network architecture is proposed with the respective comparative simulation analysis demonstrating up to 190% mean throughput improvement and 83% mean packet delay reduction compared to world’s #3 Titan CRAY XK7 High Performance Computer network configura ...
This thesis proposes new optical systems that exploit Optical Interconnect and Optical Memory Technologies and synergizes them with processors in innovative Computing Architectures for increasing bandwidth and reducing energy consumption. The novel optically-enabled concepts proposed in this thesis are spanning from complete High Performance Computing network environments down to chip-scale multi-core computing architectures. At first, OptoHPC-Sim simulation platform is demonstrated which supports the system‑scale utilization of novel electro‑optical boards and routing technologies in complete and fully operational High Performance Computing network architectures. By using OptoHPC-Sim, an optical board-based High Performance Computing network architecture is proposed with the respective comparative simulation analysis demonstrating up to 190% mean throughput improvement and 83% mean packet delay reduction compared to world’s #3 Titan CRAY XK7 High Performance Computer network configuration. Extending the use of optics from complete High Performance Computing to chip-level environments, this thesis demonstrates via physical layer simulations a complete optical cache memory layout that operates at speeds up to 16 Gb/s, which is significantly faster compared to any of the conventional technologies. The proposed cache memory layout offers a significant leap forward for optical memory technologies that by so far have been restricted to single-bit capacity layouts. This pioneering design of an optical memory layout is demonstrated to perform successfully in both Write and Read functionalities at 16 Gb/s via optical physical layer simulations using the commercially available VPI software tool. Going a step further towards highlighting the benefits of the proposed optical cache memory architecture in addressing the long-lasting “Memory Wall” problem in the computing industry, this thesis demonstrates a Chip-Multiprocessor architecture that uses the optical cache unit as a shared single-level Level-1 cache, discarding the complex cache hierarchy and offering significant speed and energy advantages to multi-core architectures. The Chip-Multiprocessor architecture is validated via Gem5 simulation engine, demonstrating that the optical cache-enabled multi-core architecture can significantly improve system performance, increase memory bandwidth and discard the need for complex coherency protocols. The simulation results suggest either an execution speed-up of 19.4% or a cache capacity requirements reduction of ~63% on average for the 12 benchmarks of PARSEC suite. Finally, in order to transfer the optical memory technology benefits from Chip Multiprocessor layouts also in novel all-optical routing table architectures, this thesis presents the first design of an all-optical Ternary-Content Addressable Memory (T‑CAM) cell and a complete optical T-CAM row architecture for use in routing look-up table implementations. The Optical T-CAM row follows a novel Wavelength Division Multiplexing encoding matchline design, providing in this way successful comparison operation for complete optical words. The proposed scheme allows for the essential subnet-masked operation that is needed in modern router applications, while its evaluation by means of physical-layer simulations reveals successful Search and Write operation at speeds of up to 20 Gb/s.
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